mirror of
https://github.com/rtlsdrblog/rtl-sdr-blog.git
synced 2024-12-28 11:58:30 +01:00
501 lines
10 KiB
C
501 lines
10 KiB
C
/*
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* Fitipower FC0013 tuner driver
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*
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* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
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* partially based on driver code from Fitipower
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* Copyright (C) 2010 Fitipower Integrated Technology Inc
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*
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* modified for use in librtlsdr
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* Copyright (C) 2012 Steve Markgraf <steve@steve-m.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include "rtlsdr_i2c.h"
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#include "tuner_fc0013.h"
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static int fc0013_writereg(void *dev, uint8_t reg, uint8_t val)
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{
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uint8_t data[2];
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data[0] = reg;
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data[1] = val;
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if (rtlsdr_i2c_write_fn(dev, FC0013_I2C_ADDR, data, 2) < 0)
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return -1;
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return 0;
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}
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static int fc0013_readreg(void *dev, uint8_t reg, uint8_t *val)
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{
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uint8_t data = reg;
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if (rtlsdr_i2c_write_fn(dev, FC0013_I2C_ADDR, &data, 1) < 0)
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return -1;
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if (rtlsdr_i2c_read_fn(dev, FC0013_I2C_ADDR, &data, 1) < 0)
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return -1;
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*val = data;
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return 0;
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}
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int fc0013_init(void *dev)
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{
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int ret = 0;
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unsigned int i;
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uint8_t reg[] = {
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0x00, /* reg. 0x00: dummy */
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0x09, /* reg. 0x01 */
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0x16, /* reg. 0x02 */
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0x00, /* reg. 0x03 */
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0x00, /* reg. 0x04 */
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0x17, /* reg. 0x05 */
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0x02, /* reg. 0x06: LPF bandwidth */
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0x0a, /* reg. 0x07: CHECK */
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0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
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Loop Bw 1/8 */
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0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */
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0xb8, /* reg. 0x0a: Disable LO Test Buffer */
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0x82, /* reg. 0x0b: CHECK */
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0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
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0x01, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, may need 0x02 */
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0x00, /* reg. 0x0e */
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0x00, /* reg. 0x0f */
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0x00, /* reg. 0x10 */
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0x00, /* reg. 0x11 */
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0x00, /* reg. 0x12 */
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0x00, /* reg. 0x13 */
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0x50, /* reg. 0x14: DVB-t High Gain, UHF.
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Middle Gain: 0x48, Low Gain: 0x40 */
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0x01, /* reg. 0x15 */
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};
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#if 0
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switch (rtlsdr_get_tuner_clock(dev)) {
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case FC_XTAL_27_MHZ:
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case FC_XTAL_28_8_MHZ:
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reg[0x07] |= 0x20;
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break;
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case FC_XTAL_36_MHZ:
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default:
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break;
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}
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#endif
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reg[0x07] |= 0x20;
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// if (dev->dual_master)
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reg[0x0c] |= 0x02;
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for (i = 1; i < sizeof(reg); i++) {
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ret = fc0013_writereg(dev, i, reg[i]);
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if (ret < 0)
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break;
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}
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return ret;
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}
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int fc0013_rc_cal_add(void *dev, int rc_val)
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{
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int ret;
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uint8_t rc_cal;
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int val;
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/* push rc_cal value, get rc_cal value */
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ret = fc0013_writereg(dev, 0x10, 0x00);
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if (ret)
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goto error_out;
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/* get rc_cal value */
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ret = fc0013_readreg(dev, 0x10, &rc_cal);
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if (ret)
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goto error_out;
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rc_cal &= 0x0f;
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val = (int)rc_cal + rc_val;
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/* forcing rc_cal */
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ret = fc0013_writereg(dev, 0x0d, 0x11);
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if (ret)
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goto error_out;
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/* modify rc_cal value */
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if (val > 15)
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ret = fc0013_writereg(dev, 0x10, 0x0f);
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else if (val < 0)
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ret = fc0013_writereg(dev, 0x10, 0x00);
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else
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ret = fc0013_writereg(dev, 0x10, (uint8_t)val);
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error_out:
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return ret;
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}
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int fc0013_rc_cal_reset(void *dev)
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{
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int ret;
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ret = fc0013_writereg(dev, 0x0d, 0x01);
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if (!ret)
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ret = fc0013_writereg(dev, 0x10, 0x00);
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return ret;
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}
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static int fc0013_set_vhf_track(void *dev, uint32_t freq)
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{
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int ret;
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uint8_t tmp;
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ret = fc0013_readreg(dev, 0x1d, &tmp);
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if (ret)
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goto error_out;
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tmp &= 0xe3;
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if (freq <= 177500000) { /* VHF Track: 7 */
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ret = fc0013_writereg(dev, 0x1d, tmp | 0x1c);
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} else if (freq <= 184500000) { /* VHF Track: 6 */
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ret = fc0013_writereg(dev, 0x1d, tmp | 0x18);
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} else if (freq <= 191500000) { /* VHF Track: 5 */
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ret = fc0013_writereg(dev, 0x1d, tmp | 0x14);
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} else if (freq <= 198500000) { /* VHF Track: 4 */
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ret = fc0013_writereg(dev, 0x1d, tmp | 0x10);
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} else if (freq <= 205500000) { /* VHF Track: 3 */
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ret = fc0013_writereg(dev, 0x1d, tmp | 0x0c);
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} else if (freq <= 219500000) { /* VHF Track: 2 */
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ret = fc0013_writereg(dev, 0x1d, tmp | 0x08);
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} else if (freq < 300000000) { /* VHF Track: 1 */
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ret = fc0013_writereg(dev, 0x1d, tmp | 0x04);
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} else { /* UHF and GPS */
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ret = fc0013_writereg(dev, 0x1d, tmp | 0x1c);
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}
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error_out:
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return ret;
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}
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int fc0013_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
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{
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int i, ret = 0;
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uint8_t reg[7], am, pm, multi, tmp;
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uint64_t f_vco;
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uint32_t xtal_freq_div_2;
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uint16_t xin, xdiv;
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int vco_select = 0;
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xtal_freq_div_2 = rtlsdr_get_tuner_clock(dev) / 2;
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/* set VHF track */
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ret = fc0013_set_vhf_track(dev, freq);
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if (ret)
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goto exit;
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if (freq < 300000000) {
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/* enable VHF filter */
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ret = fc0013_readreg(dev, 0x07, &tmp);
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if (ret)
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goto exit;
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ret = fc0013_writereg(dev, 0x07, tmp | 0x10);
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if (ret)
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goto exit;
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/* disable UHF & disable GPS */
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ret = fc0013_readreg(dev, 0x14, &tmp);
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if (ret)
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goto exit;
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ret = fc0013_writereg(dev, 0x14, tmp & 0x1f);
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if (ret)
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goto exit;
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} else if (freq <= 862000000) {
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/* disable VHF filter */
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ret = fc0013_readreg(dev, 0x07, &tmp);
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if (ret)
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goto exit;
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ret = fc0013_writereg(dev, 0x07, tmp & 0xef);
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if (ret)
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goto exit;
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/* enable UHF & disable GPS */
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ret = fc0013_readreg(dev, 0x14, &tmp);
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if (ret)
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goto exit;
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ret = fc0013_writereg(dev, 0x14, (tmp & 0x1f) | 0x40);
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if (ret)
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goto exit;
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} else {
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/* disable VHF filter */
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ret = fc0013_readreg(dev, 0x07, &tmp);
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if (ret)
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goto exit;
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ret = fc0013_writereg(dev, 0x07, tmp & 0xef);
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if (ret)
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goto exit;
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/* disable UHF & enable GPS */
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ret = fc0013_readreg(dev, 0x14, &tmp);
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if (ret)
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goto exit;
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ret = fc0013_writereg(dev, 0x14, (tmp & 0x1f) | 0x20);
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if (ret)
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goto exit;
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}
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/* select frequency divider and the frequency of VCO */
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if (freq < 37084000) { /* freq * 96 < 3560000000 */
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multi = 96;
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reg[5] = 0x82;
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reg[6] = 0x00;
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} else if (freq < 55625000) { /* freq * 64 < 3560000000 */
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multi = 64;
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reg[5] = 0x02;
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reg[6] = 0x02;
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} else if (freq < 74167000) { /* freq * 48 < 3560000000 */
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multi = 48;
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reg[5] = 0x42;
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reg[6] = 0x00;
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} else if (freq < 111250000) { /* freq * 32 < 3560000000 */
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multi = 32;
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reg[5] = 0x82;
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reg[6] = 0x02;
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} else if (freq < 148334000) { /* freq * 24 < 3560000000 */
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multi = 24;
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reg[5] = 0x22;
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reg[6] = 0x00;
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} else if (freq < 222500000) { /* freq * 16 < 3560000000 */
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multi = 16;
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reg[5] = 0x42;
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reg[6] = 0x02;
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} else if (freq < 296667000) { /* freq * 12 < 3560000000 */
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multi = 12;
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reg[5] = 0x12;
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reg[6] = 0x00;
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} else if (freq < 445000000) { /* freq * 8 < 3560000000 */
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multi = 8;
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reg[5] = 0x22;
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reg[6] = 0x02;
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} else if (freq < 593334000) { /* freq * 6 < 3560000000 */
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multi = 6;
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reg[5] = 0x0a;
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reg[6] = 0x00;
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} else if (freq < 950000000) { /* freq * 4 < 3800000000 */
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multi = 4;
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reg[5] = 0x12;
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reg[6] = 0x02;
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} else {
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multi = 2;
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reg[5] = 0x0a;
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reg[6] = 0x02;
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}
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f_vco = freq * multi;
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if (f_vco >= 3060000000U) {
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reg[6] |= 0x08;
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vco_select = 1;
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}
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/* From divided value (XDIV) determined the FA and FP value */
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xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
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if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
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xdiv++;
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pm = (uint8_t)(xdiv / 8);
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am = (uint8_t)(xdiv - (8 * pm));
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if (am < 2) {
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am += 8;
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pm--;
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}
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if (pm > 31) {
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reg[1] = am + (8 * (pm - 31));
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reg[2] = 31;
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} else {
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reg[1] = am;
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reg[2] = pm;
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}
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if ((reg[1] > 15) || (reg[2] < 0x0b)) {
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fprintf(stderr, "[FC0013] no valid PLL combination "
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"found for %u Hz!\n", freq);
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return -1;
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}
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/* fix clock out */
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reg[6] |= 0x20;
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/* From VCO frequency determines the XIN ( fractional part of Delta
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Sigma PLL) and divided value (XDIV) */
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xin = (uint16_t)((f_vco - (f_vco / xtal_freq_div_2) * xtal_freq_div_2) / 1000);
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xin = (xin << 15) / (xtal_freq_div_2 / 1000);
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if (xin >= 16384)
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xin += 32768;
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reg[3] = xin >> 8;
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reg[4] = xin & 0xff;
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reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
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switch (bandwidth) {
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case 6000000:
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reg[6] |= 0x80;
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break;
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case 7000000:
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reg[6] |= 0x40;
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break;
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case 8000000:
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default:
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break;
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}
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/* modified for Realtek demod */
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reg[5] |= 0x07;
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for (i = 1; i <= 6; i++) {
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ret = fc0013_writereg(dev, i, reg[i]);
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if (ret)
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goto exit;
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}
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ret = fc0013_readreg(dev, 0x11, &tmp);
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if (ret)
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goto exit;
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if (multi == 64)
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ret = fc0013_writereg(dev, 0x11, tmp | 0x04);
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else
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ret = fc0013_writereg(dev, 0x11, tmp & 0xfb);
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if (ret)
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goto exit;
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/* VCO Calibration */
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ret = fc0013_writereg(dev, 0x0e, 0x80);
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if (!ret)
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ret = fc0013_writereg(dev, 0x0e, 0x00);
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/* VCO Re-Calibration if needed */
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if (!ret)
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ret = fc0013_writereg(dev, 0x0e, 0x00);
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if (!ret) {
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// msleep(10);
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ret = fc0013_readreg(dev, 0x0e, &tmp);
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}
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if (ret)
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goto exit;
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/* vco selection */
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tmp &= 0x3f;
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if (vco_select) {
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if (tmp > 0x3c) {
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reg[6] &= ~0x08;
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ret = fc0013_writereg(dev, 0x06, reg[6]);
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if (!ret)
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ret = fc0013_writereg(dev, 0x0e, 0x80);
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if (!ret)
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ret = fc0013_writereg(dev, 0x0e, 0x00);
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}
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} else {
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if (tmp < 0x02) {
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reg[6] |= 0x08;
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ret = fc0013_writereg(dev, 0x06, reg[6]);
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if (!ret)
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ret = fc0013_writereg(dev, 0x0e, 0x80);
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if (!ret)
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ret = fc0013_writereg(dev, 0x0e, 0x00);
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}
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}
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exit:
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return ret;
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}
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int fc0013_set_gain_mode(void *dev, int manual)
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{
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int ret = 0;
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uint8_t tmp = 0;
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ret |= fc0013_readreg(dev, 0x0d, &tmp);
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if (manual)
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tmp |= (1 << 3);
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else
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tmp &= ~(1 << 3);
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ret |= fc0013_writereg(dev, 0x0d, tmp);
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/* set a fixed IF-gain for now */
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ret |= fc0013_writereg(dev, 0x13, 0x0a);
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return ret;
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}
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int fc0013_lna_gains[] ={
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-99, 0x02,
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-73, 0x03,
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-65, 0x05,
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-63, 0x04,
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-63, 0x00,
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-60, 0x07,
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-58, 0x01,
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-54, 0x06,
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58, 0x0f,
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61, 0x0e,
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63, 0x0d,
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65, 0x0c,
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67, 0x0b,
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68, 0x0a,
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70, 0x09,
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71, 0x08,
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179, 0x17,
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181, 0x16,
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182, 0x15,
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184, 0x14,
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186, 0x13,
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188, 0x12,
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191, 0x11,
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197, 0x10
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};
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#define GAIN_CNT (sizeof(fc0013_lna_gains) / sizeof(int) / 2)
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int fc0013_set_lna_gain(void *dev, int gain)
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{
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int ret = 0;
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unsigned int i;
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uint8_t tmp = 0;
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ret |= fc0013_readreg(dev, 0x14, &tmp);
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/* mask bits off */
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tmp &= 0xe0;
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for (i = 0; i < GAIN_CNT; i++) {
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if ((fc0013_lna_gains[i*2] >= gain) || (i+1 == GAIN_CNT)) {
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tmp |= fc0013_lna_gains[i*2 + 1];
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break;
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}
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}
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/* set gain */
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ret |= fc0013_writereg(dev, 0x14, tmp);
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return ret;
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}
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