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223 lines
5.7 KiB
C
223 lines
5.7 KiB
C
#ifndef _E4K_TUNER_H
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#define _E4K_TUNER_H
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/*
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* Elonics E4000 tuner driver
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*
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* (C) 2011-2012 by Harald Welte <laforge@gnumonks.org>
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* (C) 2012 by Sylvain Munaut <tnt@246tNt.com>
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* (C) 2012 by Hoernchen <la@tfc-server.de>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define E4K_I2C_ADDR 0xc8
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#define E4K_CHECK_ADDR 0x02
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#define E4K_CHECK_VAL 0x40
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enum e4k_reg {
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E4K_REG_MASTER1 = 0x00,
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E4K_REG_MASTER2 = 0x01,
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E4K_REG_MASTER3 = 0x02,
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E4K_REG_MASTER4 = 0x03,
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E4K_REG_MASTER5 = 0x04,
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E4K_REG_CLK_INP = 0x05,
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E4K_REG_REF_CLK = 0x06,
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E4K_REG_SYNTH1 = 0x07,
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E4K_REG_SYNTH2 = 0x08,
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E4K_REG_SYNTH3 = 0x09,
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E4K_REG_SYNTH4 = 0x0a,
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E4K_REG_SYNTH5 = 0x0b,
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E4K_REG_SYNTH6 = 0x0c,
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E4K_REG_SYNTH7 = 0x0d,
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E4K_REG_SYNTH8 = 0x0e,
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E4K_REG_SYNTH9 = 0x0f,
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E4K_REG_FILT1 = 0x10,
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E4K_REG_FILT2 = 0x11,
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E4K_REG_FILT3 = 0x12,
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// gap
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E4K_REG_GAIN1 = 0x14,
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E4K_REG_GAIN2 = 0x15,
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E4K_REG_GAIN3 = 0x16,
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E4K_REG_GAIN4 = 0x17,
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// gap
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E4K_REG_AGC1 = 0x1a,
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E4K_REG_AGC2 = 0x1b,
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E4K_REG_AGC3 = 0x1c,
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E4K_REG_AGC4 = 0x1d,
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E4K_REG_AGC5 = 0x1e,
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E4K_REG_AGC6 = 0x1f,
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E4K_REG_AGC7 = 0x20,
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E4K_REG_AGC8 = 0x21,
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// gap
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E4K_REG_AGC11 = 0x24,
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E4K_REG_AGC12 = 0x25,
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// gap
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E4K_REG_DC1 = 0x29,
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E4K_REG_DC2 = 0x2a,
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E4K_REG_DC3 = 0x2b,
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E4K_REG_DC4 = 0x2c,
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E4K_REG_DC5 = 0x2d,
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E4K_REG_DC6 = 0x2e,
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E4K_REG_DC7 = 0x2f,
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E4K_REG_DC8 = 0x30,
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// gap
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E4K_REG_QLUT0 = 0x50,
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E4K_REG_QLUT1 = 0x51,
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E4K_REG_QLUT2 = 0x52,
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E4K_REG_QLUT3 = 0x53,
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// gap
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E4K_REG_ILUT0 = 0x60,
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E4K_REG_ILUT1 = 0x61,
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E4K_REG_ILUT2 = 0x62,
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E4K_REG_ILUT3 = 0x63,
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// gap
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E4K_REG_DCTIME1 = 0x70,
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E4K_REG_DCTIME2 = 0x71,
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E4K_REG_DCTIME3 = 0x72,
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E4K_REG_DCTIME4 = 0x73,
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E4K_REG_PWM1 = 0x74,
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E4K_REG_PWM2 = 0x75,
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E4K_REG_PWM3 = 0x76,
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E4K_REG_PWM4 = 0x77,
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E4K_REG_BIAS = 0x78,
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E4K_REG_CLKOUT_PWDN = 0x7a,
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E4K_REG_CHFILT_CALIB = 0x7b,
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E4K_REG_I2C_REG_ADDR = 0x7d,
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// FIXME
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};
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#define E4K_MASTER1_RESET (1 << 0)
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#define E4K_MASTER1_NORM_STBY (1 << 1)
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#define E4K_MASTER1_POR_DET (1 << 2)
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#define E4K_SYNTH1_PLL_LOCK (1 << 0)
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#define E4K_SYNTH1_BAND_SHIF 1
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#define E4K_SYNTH7_3PHASE_EN (1 << 3)
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#define E4K_SYNTH8_VCOCAL_UPD (1 << 2)
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#define E4K_FILT3_DISABLE (1 << 5)
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#define E4K_AGC1_LIN_MODE (1 << 4)
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#define E4K_AGC1_LNA_UPDATE (1 << 5)
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#define E4K_AGC1_LNA_G_LOW (1 << 6)
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#define E4K_AGC1_LNA_G_HIGH (1 << 7)
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#define E4K_AGC6_LNA_CAL_REQ (1 << 4)
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#define E4K_AGC7_MIX_GAIN_AUTO (1 << 0)
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#define E4K_AGC7_GAIN_STEP_5dB (1 << 5)
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#define E4K_AGC8_SENS_LIN_AUTO (1 << 0)
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#define E4K_AGC11_LNA_GAIN_ENH (1 << 0)
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#define E4K_DC1_CAL_REQ (1 << 0)
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#define E4K_DC5_I_LUT_EN (1 << 0)
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#define E4K_DC5_Q_LUT_EN (1 << 1)
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#define E4K_DC5_RANGE_DET_EN (1 << 2)
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#define E4K_DC5_RANGE_EN (1 << 3)
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#define E4K_DC5_TIMEVAR_EN (1 << 4)
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#define E4K_CLKOUT_DISABLE 0x96
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#define E4K_CHFCALIB_CMD (1 << 0)
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#define E4K_AGC1_MOD_MASK 0xF
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enum e4k_agc_mode {
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E4K_AGC_MOD_SERIAL = 0x0,
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E4K_AGC_MOD_IF_PWM_LNA_SERIAL = 0x1,
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E4K_AGC_MOD_IF_PWM_LNA_AUTONL = 0x2,
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E4K_AGC_MOD_IF_PWM_LNA_SUPERV = 0x3,
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E4K_AGC_MOD_IF_SERIAL_LNA_PWM = 0x4,
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E4K_AGC_MOD_IF_PWM_LNA_PWM = 0x5,
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E4K_AGC_MOD_IF_DIG_LNA_SERIAL = 0x6,
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E4K_AGC_MOD_IF_DIG_LNA_AUTON = 0x7,
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E4K_AGC_MOD_IF_DIG_LNA_SUPERV = 0x8,
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E4K_AGC_MOD_IF_SERIAL_LNA_AUTON = 0x9,
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E4K_AGC_MOD_IF_SERIAL_LNA_SUPERV = 0xa,
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};
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enum e4k_band {
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E4K_BAND_VHF2 = 0,
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E4K_BAND_VHF3 = 1,
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E4K_BAND_UHF = 2,
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E4K_BAND_L = 3,
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};
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enum e4k_mixer_filter_bw {
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E4K_F_MIX_BW_27M = 0,
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E4K_F_MIX_BW_4M6 = 8,
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E4K_F_MIX_BW_4M2 = 9,
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E4K_F_MIX_BW_3M8 = 10,
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E4K_F_MIX_BW_3M4 = 11,
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E4K_F_MIX_BW_3M = 12,
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E4K_F_MIX_BW_2M7 = 13,
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E4K_F_MIX_BW_2M3 = 14,
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E4K_F_MIX_BW_1M9 = 15,
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};
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enum e4k_if_filter {
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E4K_IF_FILTER_MIX,
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E4K_IF_FILTER_CHAN,
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E4K_IF_FILTER_RC
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};
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struct e4k_pll_params {
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uint32_t fosc;
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uint32_t intended_flo;
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uint32_t flo;
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uint16_t x;
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uint8_t z;
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uint8_t r;
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uint8_t r_idx;
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uint8_t threephase;
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};
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struct e4k_state {
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void *i2c_dev;
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uint8_t i2c_addr;
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enum e4k_band band;
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struct e4k_pll_params vco;
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void *rtl_dev;
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};
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int e4k_init(struct e4k_state *e4k);
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int e4k_standby(struct e4k_state *e4k, int enable);
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int e4k_if_gain_set(struct e4k_state *e4k, uint8_t stage, int8_t value);
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int e4k_mixer_gain_set(struct e4k_state *e4k, int8_t value);
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int e4k_commonmode_set(struct e4k_state *e4k, int8_t value);
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int e4k_tune_freq(struct e4k_state *e4k, uint32_t freq);
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int e4k_tune_params(struct e4k_state *e4k, struct e4k_pll_params *p);
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uint32_t e4k_compute_pll_params(struct e4k_pll_params *oscp, uint32_t fosc, uint32_t intended_flo);
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int e4k_if_filter_bw_get(struct e4k_state *e4k, enum e4k_if_filter filter);
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int e4k_if_filter_bw_set(struct e4k_state *e4k, enum e4k_if_filter filter,
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uint32_t bandwidth);
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int e4k_if_filter_chan_enable(struct e4k_state *e4k, int on);
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int e4k_rf_filter_set(struct e4k_state *e4k);
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int e4k_manual_dc_offset(struct e4k_state *e4k, int8_t iofs, int8_t irange, int8_t qofs, int8_t qrange);
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int e4k_dc_offset_calibrate(struct e4k_state *e4k);
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int e4k_dc_offset_gen_table(struct e4k_state *e4k);
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int e4k_set_lna_gain(struct e4k_state *e4k, int32_t gain);
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int e4k_enable_manual_gain(struct e4k_state *e4k, uint8_t manual);
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int e4k_set_enh_gain(struct e4k_state *e4k, int32_t gain);
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#endif /* _E4K_TUNER_H */
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