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init: disable 4 MHz clock output

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The pin where this clock is outputted is quite close to the
ADC inputs, so better disable it.

Signed-off-by: Steve Markgraf <steve@steve-m.de>
This commit is contained in:
Steve Markgraf 2012-06-22 15:52:35 +02:00
parent b09628b3e8
commit fc736ae67f
1 changed files with 3 additions and 0 deletions
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3
src/librtlsdr.c
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@ -496,6 +496,9 @@ void rtlsdr_init_baseband(rtlsdr_dev_t *dev)
/* Enable Zero-IF mode (en_bbin bit), DC cancellation (en_dc_est), /* Enable Zero-IF mode (en_bbin bit), DC cancellation (en_dc_est),
* IQ estimation/compensation (en_iq_comp, en_iq_est) */ * IQ estimation/compensation (en_iq_comp, en_iq_est) */
rtlsdr_demod_write_reg(dev, 1, 0xb1, 0x1b, 1); rtlsdr_demod_write_reg(dev, 1, 0xb1, 0x1b, 1);
/* disable 4.096 MHz clock output on pin TP_CK0 */
rtlsdr_demod_write_reg(dev, 0, 0x0d, 0x83, 1);
} }
int rtlsdr_deinit_baseband(rtlsdr_dev_t *dev) int rtlsdr_deinit_baseband(rtlsdr_dev_t *dev)