mirror of
https://github.com/rtlsdrblog/rtl-sdr-blog.git
synced 2025-01-06 16:27:16 +01:00
311 lines
8.8 KiB
C
311 lines
8.8 KiB
C
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/*
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* fc0012 tuner support for rtl-sdr
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*
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* Based on tuner_fc0012.c found as part of the (seemingly GPLed)
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* rtl2832u Linux DVB driver.
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*
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* Rewritten and hacked into rtl-sdr by David Basden <davidb-sdr@rcpt.to>
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include "tuner_fc0012.h"
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#include "i2c.h"
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#define CRYSTAL_FREQ 28800000
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#define FC0012_LNAGAIN FC0012_LNA_GAIN_HI
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/* Incomplete list of register settings:
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*
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* Name Reg Bits Desc
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* LNA_POWER_DOWN 0x06 0 Set to 1 to switch off low noise amp
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* VCO_SPEED 0x06 3 Set the speed of the VCO. example
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* driver hardcodes to 1 for some reason
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* BANDWIDTH 0x06 6-7 Set bandwidth. 6MHz = 0x80, 7MHz=0x40
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* 8MHz=0x00
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* XTAL_SPEED 0x07 5 Set to 1 for 28.8MHz Crystal input
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* or 0 for 36MHz
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* EN_CAL_RSSI 0x09 4 Enable calibrate RSSI
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* (Receive Signal Strength Indicator)
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* LNA_FORCE 0x0d 0
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* AGC_FORCE 0x0d ?
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* LNA_GAIN 0x13 0-4 Low noise amp gain
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* LNA_COMPS 0x15 3 ?
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* VCO_CALIB 0x0e 7 Set high then low to calibrate VCO
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*
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*/
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/* glue functions to rtl-sdr code */
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int FC0012_Write(void *pTuner, unsigned char RegAddr, unsigned char Byte)
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{
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uint8_t data[2];
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data[0] = RegAddr;
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data[1] = Byte;
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if (rtlsdr_i2c_write((rtlsdr_dev_t *)pTuner, FC0012_I2C_ADDR, data, 2) < 0)
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return FC0012_ERROR;
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return FC0012_OK;
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}
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int FC0012_Read(void *pTuner, unsigned char RegAddr, unsigned char *pByte)
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{
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uint8_t data = RegAddr;
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if (rtlsdr_i2c_write((rtlsdr_dev_t *)pTuner, FC0012_I2C_ADDR, &data, 1) < 0)
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return FC0012_ERROR;
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if (rtlsdr_i2c_read((rtlsdr_dev_t *)pTuner, FC0012_I2C_ADDR, &data, 1) < 0)
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return FC0012_ERROR;
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*pByte = data;
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return FC0012_OK;
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}
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#ifdef DEBUG
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#define DEBUGF printf
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#else
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#define DEBUGF(...) ()
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#endif
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#if 0
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void FC0012_Dump_Registers()
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{
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#ifdef DEBUG
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unsigned char regBuf;
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int ret;
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int i;
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DEBUGF("\nFC0012 registers:\n");
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for (i=0; i<=0x15; ++i)
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{
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ret = FC0012_Read(pTuner, i, ®Buf);
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if (ret) DEBUGF("\nCouldn't read register %02x\n", i);
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DEBUGF("R%x=%02x ",i,regBuf);
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}
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DEBUGF("\n");
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FC0012_Read(pTuner, 0x06, ®Buf);
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DEBUGF("LNA_POWER_DOWN:\t%s\n", regBuf & 1 ? "Powered down" : "Not Powered Down");
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DEBUGF("VCO_SPEED:\t%s\n", regBuf & 0x8 ? "High speed" : "Slow speed");
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DEBUGF("Bandwidth:\t%s\n", (regBuf & 0xC) ? "8MHz" : "less than 8MHz");
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FC0012_Read(pTuner, 0x07, ®Buf);
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DEBUGF("Crystal Speed:\t%s\n", (regBuf & 0x20) ? "28.8MHz" : "36MHZ<!>");
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FC0012_Read(pTuner, 0x09, ®Buf);
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DEBUGF("RSSI calibration mode:\t%s\n", (regBuf & 0x10) ? "RSSI CALIBRATION IN PROGRESS<!>" : "Disabled");
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FC0012_Read(pTuner, 0x0d, ®Buf);
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DEBUGF("LNA Force:\t%s\n", (regBuf & 0x1) ? "Forced" : "Not Forced");
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FC0012_Read(pTuner, 0x13, ®Buf);
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DEBUGF("LNA Gain:\t");
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switch (regBuf) {
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case (0x10): DEBUGF("19.7dB\n"); break;
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case (0x17): DEBUGF("17.9dB\n"); break;
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case (0x08): DEBUGF("7.1dB\n"); break;
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case (0x02): DEBUGF("-9.9dB\n"); break;
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default: DEBUGF("unknown gain value 0x02x\n");
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}
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#endif
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}
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#endif
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int FC0012_Open(void *pTuner)
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{
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// DEBUGF("FC0012_Open start");
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if (FC0012_Write(pTuner, 0x01, 0x05)) return -1;
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if (FC0012_Write(pTuner, 0x02, 0x10)) return -1;
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if (FC0012_Write(pTuner, 0x03, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x04, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x05, 0x0F)) return -1;
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if (FC0012_Write(pTuner, 0x06, 0x00)) return -1; // divider 2, VCO slow
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if (FC0012_Write(pTuner, 0x07, 0x20)) return -1; // change to 0x00 for a 36MHz crystal
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if (FC0012_Write(pTuner, 0x08, 0xFF)) return -1; // AGC Clock divide by 254, AGC gain 1/256, Loop Bw 1/8
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if (FC0012_Write(pTuner, 0x09, 0x6E)) return -1; // Disable LoopThrough
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if (FC0012_Write(pTuner, 0x0A, 0xB8)) return -1; // Disable LO Test Buffer
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if (FC0012_Write(pTuner, 0x0B, 0x82)) return -1; // Output Clock is same as clock frequency
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//if (FC0012_Write(pTuner, 0x0C, 0xF8)) return -1;
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if (FC0012_Write(pTuner, 0x0C, 0xFC)) return -1; // AGC up-down mode
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if (FC0012_Write(pTuner, 0x0D, 0x02)) return -1; // AGC Not Forcing & LNA Forcing
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if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x0F, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x10, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x11, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x12, 0x1F)) return -1; // Set to maximum gain
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if (FC0012_Write(pTuner, 0x13, FC0012_LNAGAIN)) return -1;
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if (FC0012_Write(pTuner, 0x14, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x15, 0x04)) return -1; // Enable LNA COMPS
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/* Black magic from nim_rtl2832_fc0012.c in DVB driver.
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Even though we've set 0x11 to 0x00 above, this needs to happen to have
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it go back
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*/
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if (FC0012_Write(pTuner, 0x0d, 0x02)) return -1;
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if (FC0012_Write(pTuner, 0x11, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x15, 0x04)) return -1;
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// DEBUGF("FC0012_Open SUCCESS");
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return FC0012_OK;
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}
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# if 0
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// Frequency is in kHz. Bandwidth is in MHz
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// This is pseudocode to set GPIO6 for VHF/UHF filter switching.
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// Trying to do this in reality leads to fail currently. I'm probably doing it wrong.
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void FC0012_Frequency_Control(unsigned int Frequency, unsigned short Bandwidth)
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{
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if( Frequency < 260000 && Frequency > 150000 )
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{
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// set GPIO6 = low
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// 1. Set tuner frequency
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// 2. if the program quality is not good enough, switch to frequency + 500kHz
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// 3. if the program quality is still no good, switch to frequency - 500kHz
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}
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else
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{
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// set GPIO6 = high
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// set tuner frequency
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}
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}
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#endif
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int FC0012_SetFrequency(void *pTuner, unsigned long Frequency, unsigned short Bandwidth)
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{
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int VCO1 = 0;
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unsigned long doubleVCO;
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unsigned short xin, xdiv;
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unsigned char reg[21], am, pm, multi;
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unsigned char read_byte;
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unsigned long CrystalFreqKhz;
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// DEBUGF("FC0012_SetFrequency start");
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CrystalFreqKhz = (CRYSTAL_FREQ + 500) / 1000;
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//===================================== Select frequency divider and the frequency of VCO
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if (Frequency * 96 < 3560000)
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{
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multi = 96; reg[5] = 0x82; reg[6] = 0x00;
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}
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else if (Frequency * 64 < 3560000)
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{
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multi = 64; reg[5] = 0x82; reg[6] = 0x02;
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}
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else if (Frequency * 48 < 3560000)
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{
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multi = 48; reg[5] = 0x42; reg[6] = 0x00;
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}
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else if (Frequency * 32 < 3560000)
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{
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multi = 32; reg[5] = 0x42; reg[6] = 0x02;
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}
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else if (Frequency * 24 < 3560000)
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{
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multi = 24; reg[5] = 0x22; reg[6] = 0x00;
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}
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else if (Frequency * 16 < 3560000)
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{
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multi = 16; reg[5] = 0x22; reg[6] = 0x02;
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}
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else if (Frequency * 12 < 3560000)
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{
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multi = 12; reg[5] = 0x12; reg[6] = 0x00;
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}
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else if (Frequency * 8 < 3560000)
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{
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multi = 8; reg[5] = 0x12; reg[6] = 0x02;
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}
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else if (Frequency * 6 < 3560000)
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{
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multi = 6; reg[5] = 0x0A; reg[6] = 0x00;
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}
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else
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{
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multi = 4; reg[5] = 0x0A; reg[6] = 0x02;
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}
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doubleVCO = Frequency * multi;
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reg[6] = reg[6] | 0x08;
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VCO1 = 1;
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xdiv = (unsigned short)(doubleVCO / (CrystalFreqKhz / 2));
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if( (doubleVCO - xdiv * (CrystalFreqKhz / 2)) >= (CrystalFreqKhz / 4) )
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xdiv = xdiv + 1;
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pm = (unsigned char)( xdiv / 8 );
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am = (unsigned char)( xdiv - (8 * pm));
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if (am < 2) {
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reg[1] = am + 8;
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reg[2] = pm - 1;
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} else {
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reg[1] = am;
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reg[2] = pm;
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}
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// From VCO frequency determines the XIN ( fractional part of Delta Sigma PLL) and divided value (XDIV).
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xin = (unsigned short)(doubleVCO - ((unsigned short)(doubleVCO / (CrystalFreqKhz / 2))) * (CrystalFreqKhz / 2));
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xin = ((xin << 15)/(unsigned short)(CrystalFreqKhz / 2));
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if( xin >= (unsigned short) 16384 )
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xin = xin + (unsigned short) 32768;
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reg[3] = (unsigned char)(xin >> 8);
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reg[4] = (unsigned char)(xin & 0x00FF);
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// DEBUGF("Frequency: %lu, Fa: %d, Fp: %d, Xin:%d \n", Frequency, am, pm, xin);
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switch(Bandwidth)
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{
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case 6: reg[6] = 0x80 | reg[6]; break;
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case 7: reg[6] = (~0x80 & reg[6]) | 0x40; break;
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case 8: default: reg[6] = ~0xC0 & reg[6]; break;
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}
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if (FC0012_Write(pTuner, 0x01, reg[1])) return -1;
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if (FC0012_Write(pTuner, 0x02, reg[2])) return -1;
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if (FC0012_Write(pTuner, 0x03, reg[3])) return -1;
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if (FC0012_Write(pTuner, 0x04, reg[4])) return -1;
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//reg[5] = reg[5] | 0x07; // This is really not cool. Why is it there?
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// Same with hardcoding VCO=1
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if (FC0012_Write(pTuner, 0x05, reg[5])) return -1;
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if (FC0012_Write(pTuner, 0x06, reg[6])) return -1;
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// VCO Calibration
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if (FC0012_Write(pTuner, 0x0E, 0x80)) return -1;
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if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
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// VCO Re-Calibration if needed
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if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
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if (FC0012_Read(pTuner, 0x0E, &read_byte)) return -1;
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reg[14] = 0x3F & read_byte;
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if (VCO1)
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{
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if (reg[14] > 0x3C)
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{
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reg[6] = 0x08 | reg[6];
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if (FC0012_Write(pTuner, 0x06, reg[6])) return -1;
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if (FC0012_Write(pTuner, 0x0E, 0x80)) return -1;
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if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
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}
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}
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else
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{
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if (reg[14] < 0x02) {
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reg[6] = 0x08 | reg[6];
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if (FC0012_Write(pTuner, 0x06, reg[6])) return -1;
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if (FC0012_Write(pTuner, 0x0E, 0x80)) return -1;
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if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
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}
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}
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// DEBUGF("FC0012_SetFrequency SUCCESS"); FC0012_Dump_Registers();
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return FC0012_OK;
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}
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