mirror/rtl-sdr-blog
1
0
Fork 0
mirror of https://github.com/rtlsdrblog/rtl-sdr-blog.git synced 2024-11-10 04:37:37 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

tuner_fc001x: fix tuning for frequencies < 45 MHz

Browse Source 
This allows tuning to 27 MHz for example (civil band).
Best results are achieved when setting the gain to
very low values.

Signed-off-by: Steve Markgraf <steve@steve-m.de>
This commit is contained in:
Steve Markgraf 2012-10-03 17:19:29 +02:00
parent b4e48d9555
commit 18687916d6
2 changed files with 42 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
src/tuner_fc0012.c
View File

@ -206,37 +206,31 @@ int fc0012_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
vco_select = 1;
}
if (freq >= 45000000) {
/* From divided value (XDIV) determined the FA and FP value */
xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
xdiv++;
/* From divided value (XDIV) determined the FA and FP value */
xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
xdiv++;
pm = (uint8_t)(xdiv / 8);
am = (uint8_t)(xdiv - (8 * pm));
pm = (uint8_t)(xdiv / 8);
am = (uint8_t)(xdiv - (8 * pm));
if (am < 2) {
am += 8;
pm--;
}
if (am < 2) {
am += 8;
pm--;
}
if (pm > 31) {
reg[1] = am + (8 * (pm - 31));
reg[2] = 31;
} else {
reg[1] = am;
reg[2] = pm;
}
if (reg[1] > 15) {
fprintf(stderr, "[FC0012] no valid PLL combination "
"found for %u Hz!\n", freq);
return -1;
}
if (pm > 31) {
reg[1] = am + (8 * (pm - 31));
reg[2] = 31;
} else {
/* fix for frequency less than 45 MHz */
reg[1] = 0x06;
reg[2] = 0x11;
reg[1] = am;
reg[2] = pm;
}
if ((reg[1] > 15) || (reg[2] < 0x0b)) {
fprintf(stderr, "[FC0012] no valid PLL combination "
"found for %u Hz!\n", freq);
return -1;
}
/* fix clock out */

48
src/tuner_fc0013.c
View File

@ -311,37 +311,31 @@ int fc0013_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
vco_select = 1;
}
if (freq >= 45000000) {
/* From divided value (XDIV) determined the FA and FP value */
xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
xdiv++;
/* From divided value (XDIV) determined the FA and FP value */
xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
xdiv++;
pm = (uint8_t)(xdiv / 8);
am = (uint8_t)(xdiv - (8 * pm));
pm = (uint8_t)(xdiv / 8);
am = (uint8_t)(xdiv - (8 * pm));
if (am < 2) {
am += 8;
pm--;
}
if (am < 2) {
am += 8;
pm--;
}
if (pm > 31) {
reg[1] = am + (8 * (pm - 31));
reg[2] = 31;
} else {
reg[1] = am;
reg[2] = pm;
}
if (reg[1] > 15) {
fprintf(stderr, "[FC0013] no valid PLL combination "
"found for %u Hz!\n", freq);
return -1;
}
if (pm > 31) {
reg[1] = am + (8 * (pm - 31));
reg[2] = 31;
} else {
/* fix for frequency less than 45 MHz */
reg[1] = 0x06;
reg[2] = 0x11;
reg[1] = am;
reg[2] = pm;
}
if ((reg[1] > 15) || (reg[2] < 0x0b)) {
fprintf(stderr, "[FC0013] no valid PLL combination "
"found for %u Hz!\n", freq);
return -1;
}
/* fix clock out */